high voltage rail up to 600 v dv/dt immunity +- 50 v/nsec in full tem- perature range driver current capability: 400 ma source, 650 ma sink switching times 50/30 nsec rise/fall with 1nf load cmos/ttl schmitt trigger inputs with hysteresis and pull down shut down input dead time setting under voltage lock out integrated bootstrap diode clamping on vcc so8/minidip packages description the l6384 is an high-voltage device, manufac- tured with the bcd"off-line" technology. it has an half - bridge driver structure that enables to drive n channel power mos or igbt. the upper (floating) section is enabled to work with voltage rail up to 600v. the logic inputs are cmos/ttl compatible for ease of interfacing with controlling devices. matched delays between lower and up- per section simplify high frequency operation. dead time setting can be readily accomplished by means of an external resistor. may 2000 ? logic uv detection level shifter rs v cc lvg driver v cc in dt/sd v boot hvg driver hvg h.v. load out lvg gnd d97in518a dead time v cc idt vthi bootstrap driver c boot 4 3 5 6 7 8 1 2 block diagram so8 minidip ordering numbers: l6384d l6384 l6384 high-voltage half bridge driver 1/10
absolute maximum ratings symbol parameter value unit vout output voltage -3 to vboot -18 v vcc supply voltage (*) - 0.3 to 14.6 v is supply current (*) 25 ma vboot floating supply voltage -1 to 618 v vhvg upper gate output voltage -1 to vboot v vlvg lower gate output voltage -0.3 to vcc +0.3 v vi logic input voltage -0.3 to vcc +0.3 v vsd shut down/dead time voltage -0.3 to vcc +0.3 v dvout/dt allowed output slew rate 50 v/ns ptot total power dissipation (tj = 85 c) 750 mw tj junction temperature 150 c ts storage temperature -50 to 150 c (*) the device has an internal clamping zener between gnd and the vcc pin, it must not be supplied by a low impedence voltage s ource. note: esd immunity for pins 6, 7 and 8 is guaranteed up to 900 v (human body model) thermal data symbol parameter so8 minidip unit r th j-amb thermal resistance junction to ambient 150 100 c/w pin description n. name type function 1 in i logic input: it is in phase with hvg and in opposition of phase with lgv. it is compatible to v cc voltage. [vil max = 1.5v, vih min = 3.6v] 2 vcc i supply input voltage: there is an internal clamp [typ. 15.6v] 3 dt/sd i high impedance pin with two functionalities. when pulled lower than vdt [typ. 0.5v] the device is shut down. a voltage higher than vdt sets the dead time between high side gate driver and low side gate driver. the dead time value can be set forcing a certain voltage level on the pin or connecting a resistor between pin 3 and ground. care must be taken to avoid below threshold spikes on pin 3 that can cause undesired shut down of the ic. for this reason the connection of the components between pin 3 and ground has to be as short as possible. this pin can not be left floating for the same reason. the pin has not be pulled through a low impedance to v cc , because of the drop on the current source that feeds rdt. the operative range is: vdt....270k idt, that allows a dt range of 0.4 - 3.1 m s. 4 gnd ground in v cc dt/sd gnd 1 3 2 4 lvg vout hvg v boot 8 7 6 5 d97in519 pin connection l6384 2/10
recommended operating conditions symbol pin parameter test condition min. typ. max. unit vout 6 output voltage note1 580 v vboot - vout 8 floating supply voltage note1 17 v fsw switching frequency hv g,lvg load cl = 1nf 400 khz vcc 2 supply voltage vclamp v t j junction temperature -45 125 c note 1: if the condition vboot - vout < 18v is guaranteed, vout can range from -3 to 580v. electrical characteristics ac operation (v cc = 14.4v; tj = 25c) symbol pin parameter test condition min. typ. max. unit ton 1 vs 5,7 high/low side driver turn-on propagation delay vout = 0v r dt = 47k w 200+dt ns tonsd 3 vs 5,7 shut down input propagation delay 220 280 ns toff 1 vs 5,7 high/low side driver turn-off propagation delay vout = 0v r dt = 47k w 250 300 ns vout = 0v r dt = 146k w 200 250 ns vout = 0v r dt = 270k w 170 200 ns tr 7,5 rise time cl = 1000pf 70 ns tf 7,5 fall time cl = 1000pf 30 ns dc operation (v cc = 14.4v; tj = 25c) supply voltage section vclamp 2 supply voltage clamping is = 5ma 14.6 15.6 16.6 v vccth1 2 vcc uv turn on threshold 11.5 12 12.5 v vccth2 2 vcc uv turn off threshold 9.5 10 10.5 v n. name type function 5 lvg o low side driver output: the output stage can deliver 400ma source and 650ma sink [typ. values]. the circuit guarantees 0.3v max on the pin (@ i sink = 10ma) with v cc > 3v and lower than the turn on threshold. this allows to omit the bleeder resistor connected between the gate and the source of the external mosfet normally used to hold the pin low; the gate driver ensures low impedance also in sd conditions. 6 vout o upper driver floating reference: layout care has to be taken to avoid below ground spikes on this pin. 7 hvg o high side driver output: the output stage can deliver 400ma source and 650ma sink [typ. values]. the circuit gurantees 0.3v max between this pin and vout (@ i sink = 10ma) with v cc > 3v and lower than the turn on threshold. this allows to omit the bleeder resistor connected between the gate and the source of the external mosfet normally used to hold the pin low; the gate driver ensures low impedance also in sd conditions. 8 vboot bootstrap supply voltage: it is the upper driver floating supply. the bootstrap capacitor connected between this pin and pin 6 can be fed by an internal structure named "bootstrap driver" (a patented structure). this structure can replace the external bootstrap diode. pin description (continued) l6384 3/10
in sd hvg lvg d99in1017 figure 1. input/output timing diagram symbol pin parameter test condition min. typ. max. unit vcchys 2 vcc uv hysteresis 2 v iqccu 2 undervoltage quiescent supply current vcc 11v 150 m a iqcc 2 quiescent current vin = 0 380 500 m a bootstrapped supply voltage section vboot 8 bootstrap supply voltage 17 v iqbs quiescent current vout = vboot; in = high 200 m a ilk high voltage leakage current vhvg = vout = vboot = 600v 10 m a rdson bootstrap driver on resistance (*) vcc 3 12.5v; in = low 125 w high/low side driver iso 5,7 source short circuit current vin = vih (tp < 10 m s) 300 400 ma isi sink short circuit current vin = vil (tp < 10 m s) 500 650 ma logic inputs vil 2,3 low level logic threshold voltage 1.5 v vih high level logic threshold voltage 3.6 v iih high level logic input current vin = 15v 50 70 m a iil low level logic input current vin = 0v 1 m a iref 3 dead time setting current 28 m a dt 3 vs 5,7 dead time setting range (**) rdt = 47k rdt = 146 rdt = 270k 0.4 0.5 1.5 2.7 3.1 m s m s m s vdt 3 shutdown threshold 0.5 v (*) r dson is tested in the following way: r dson = ( v cc - v cboot1 ) - ( v cc - v cboot2 ) i 1 ( v cc, v cboot1 ) - i 2 ( v cc ,v cboot2 ) where i 1 is pin 8 current when v cboot = v cboot1 , i 2 when v cboot = v cboot2 (**) pin 3 is a high impedence pin. therefore dt can be set also forcing a certain voltage v 3 on this pin. the dead time is the same obtained with a rdt if it is: rdt iref = v 3 . dc operation (continued) l6384 4/10
bootstrap driver a bootstrap circuitry is needed to supply the high voltage section. this function is normally accom- plished by a high voltage fast recovery diode (fig. 4a). in the l6384 a patented integrated structure replaces the external diode. it is realized by a high voltage dmos, driven synchronously with the low side driver (lvg), with in series a diode, as shown in fig. 4b an internal charge pump (fig. 4b) provides the dmos driving voltage . the diode connected in series to the dmos has been added to avoid undesirable turn on of it. cboot selection and charging : to choose the proper c boot value the external mos can be seen as an equivalent capacitor. this capacitor c ext is related to the mos total gate charge : c ext = q gate v gate the ratio between the capacitors c ext and c boot is proportional to the cyclical voltage loss . it has to be: c boot >>>c ext e.g.: if q gate is 30nc and v gate is 10v, c ext is 3nf. with c boot = 100nf the drop would be 300mv. if hvg has to be supplied for a long time, the c boot selection has to take into account also the leakage losses. e.g.: hvg steady state consumption is lower than 200 m a, so if hvg t on is 5ms, c boot has to supply 1 m c to c ext . this charge on a 1 m f ca- pacitor means a voltage drop of 1v. the internal bootstrap driver gives great advan- tages: the external fast recovery diode can be avoided (it usually has great leakage current). this structure can work only if v out is close to gnd (or lower) and in the meanwhile the lvg is on. the charging time (t charge ) of the c boot is the time in which both conditions are fulfilled and it has to be long enough to charge the capacitor. the bootstrap driver introduces a voltage drop due to the dmos r dson (typical value: 125 ohm). at low frequency this drop can be ne- glected. anyway increasing the frequency it must be taken in to account. the following equation is useful to compute the drop on the bootstrap dmos: v drop = i charge r dson ? v drop = q gate t charge r dson where q gate is the gate charge of the external power mos, r dson is the on resistance of the bootstrap dmos, and t charge is the charging time of the bootstrap capacitor. for example: using a power mos with a total gate charge of 30nc the drop on the bootstrap dmos is about 1v, if the t charge is 5 m s. in fact: v drop = 30nc 5 m s 125 w ~ 0.8v v drop has to be taken into account when the voltage drop on c boot is calculated: if this drop is too high, or the circuit topology doesnt allow a sufficient charging time, an external diode can be used. for both high and low side buffers @25?c tamb 0 1 2 3 4 5 c (nf) 0 50 100 150 200 250 time (nsec) tr d99in1015 tf figure 2. typical rise and fall times vs. load capacitance 02468101214v s (v) 10 10 2 10 3 10 4 iq ( m a) d99in1016 figure 3. quiescent current vs. supply voltage l6384 5/10
50 100 150 200 250 300 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 dt ( m s) rdt (kohm) typ. @ vcc = 14.4v figure 5. dead time vs. resistance. -45 -25 0 25 50 75 100 125 t j (c) 0 0.5 1 1.5 2 2.5 3 dt (us) r=47k r=146k r=270k t y p. t y p. t y p. @ vcc = 14.4v figure 6. dead time vs. temperature. -45 -25 0 25 50 75 100 125 0 100 200 300 400 ton,toff (ns) @ rdt = 47kohm @ rdt = 146kohm @ rdt = 270kohm t j ( c ) t y p. t y p. t y p. @ vcc = 14.4v figure 7. driver propagation delay vs. temperature. -45 -25 0 25 50 75 100 125 0 0.2 0.4 0.6 0.8 1 vdt (v) t j ( c ) t y p. @ vcc = 14.4v figure 8. shutdown threshold vs. temperature to load d99in1067 h.v. hvg ab lvg hvg lvg c boot to load h.v. c boot d boot v boot v s v s v out v boot v out figure 4. bootstrap driver l6384 6/10
-45 -25 0 25 50 75 100 125 0 200 400 600 800 1000 current (ma) t j ( c ) t y p. @ vcc = 14.4v figure 11. output source current vs. tem- perature. -45 -25 0 25 50 75 100 125 0 200 400 600 800 1000 current (ma) t j ( c ) t y p. @ vcc = 14.4v figure 12. output sink current vs.temperature -45 -25 0 25 50 75 100 125 10 11 12 13 14 15 vccth1 (v) tj (c) t y p. figure 9. vcc uv turn on vs. temperature -45 -25 0 25 50 75 100 125 8 9 10 11 12 13 vccth2 (v) t j ( c ) t y p. figure 10. vcc uv turn off vs. temperature l6384 7/10
minidip dim. mm inch min. typ. max. min. typ. max. a 3.32 0.131 a1 0.51 0.020 b 1.15 1.65 0.045 0.065 b 0.356 0.55 0.014 0.022 b1 0.204 0.304 0.008 0.012 d 10.92 0.430 e 7.95 9.75 0.313 0.384 e 2.54 0.100 e3 7.62 0.300 e4 7.62 0.300 f 6.6 0.260 i 5.08 0.200 l 3.18 3.81 0.125 0.150 z 1.52 0.060 outline and mechanical data l6384 8/10
dim. mm inch min. typ. max. min. typ. max. a 1.75 0.069 a1 0.1 0.25 0.004 0.010 a2 1.65 0.065 a3 0.65 0.85 0.026 0.033 b 0.35 0.48 0.014 0.019 b1 0.19 0.25 0.007 0.010 c 0.25 0.5 0.010 0.020 c1 45 (typ.) d (1) 4.8 5.0 0.189 0.197 e 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 3.81 0.150 f (1) 3.8 4.0 0.15 0.157 l 0.4 1.27 0.016 0.050 m 0.6 0.024 s8 (max.) (1) d and f do not include mold flash or protrusions. mold flash or potrusions shall not exceed 0.15mm (.006inch). so8 outline and mechanical data l6384 9/10
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specification mentioned in this pu blication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectron ics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicr oelectronics. the st logo is a registered trademark of stmicroelectronics ? 2000 stmicroelectronics C printed in italy C all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com l6384 10/10
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